As process geometries continue to decrease and clock frequencies continue to increase, signal integrity is becoming a more significant issue for designers. It is essential for designers to address signal integrity and performance issues to ensure that their designs are functioning properly, while providing their designs to their customers in the shortest amount of time. One essential task to ensure signal integrity and performance is to provide static timing analysis, which is a point-to-point delay analysis of a design network with respect to a given set of constraints. The placement and routing of a circuit design is executed according to timing constraints that are specified in the design process. Timing analysis software then interacts with the placement and routing of the circuit to ensure that the timing constraints imposed on the design are met.
However, it is generally difficult to analyze performance of different design blocks that exist as a part of a processor block which is embedded in a programmable logic device (PLD), such as a field programmable gate array (FPGA). While standard static timing analysis tools are fast and accurate, they are generally unable to accommodate custom or semi-custom circuit blocks. That is, static timing analysis tools are primarily developed to support a pre-determined design flow. These tools also have difficulty in accommodating very large IP blocks such as a processor core. Also, formats provided by vendors may not be compatible with the requirements of the tool.
Further, each design group for the various design blocks may have a different design technique. For example, interconnect tiles surrounding a processor block are designed using custom circuit design flow and are typically verified using a circuit simulation program, such as a Simulation Program with Integrated Circuit Emphasis (SPICE). In contrast, the processor core, such as a PowerPC processor core available from IBM Corporation, is verified by the provider of the processor core. PLDs may also use a number of these predefined functions, or functional blocks, that will need to interact with the configurable logic. The interface I/O timing data for the various functional blocks is provided in a textual format by the IP provider. Because all of these blocks are interconnected together, there is a need to analyze the timing and verify the performance of the various blocks in aggregate.
Conventional methods of verifying the timing performance of the various blocks in aggregate include first individually gathering I/O timing of all of these blocks. Then, the interconnects between each block are simulated using a circuit simulator, such as SPICE. Finally, all of these timing delay numbers are added together in a spreadsheet format. In addition to being cumbersome, such conventional processes employing spreadsheets are not very accurate. Because the timing numbers are required to be calculated for a number of process/voltage/temperature (PVT) conditions, the number of combinations becomes excessive. Also, the time that is required to run SPICE simulations accurately on tens of thousands of interconnect wires is very large. Finally, after every minor design change, it takes a significant amount of time to re-verify the performance of the entire design block. For example, every iteration of a performance verification step could take one or two weeks to complete.
Accordingly, there is a need for a more efficient method of enabling timing verification.